GICv3 and aarch32
Hi, I just started to port our secure OS on an armv8 board, with a GIC-v3. The EL1 non secure OS will be the vendor Linux OS, which runs in aarch64. The EL1 secure OS will be our secure OS, which runs...
View ArticleGIC-v3: optional asymetric / legacy support
Hi, how can I check if the GIC-v3 I am using has support for the optional asymetric / legacy support ? Best, V.
View ArticleCan't build a simplest project with Code::Block IDE
Hello, I've met problems while building project with Code::Block IDE, that is setup for GNU Tools ARM Embedded 5.4 2016q3. Here is build log. arm-none-eabi-g++.exe -L"C:\Program Files (x86)\GNU...
View ArticleGIC-400 address layout in deviation from standard?
Dear all, It seems there are some GIC-400 implementations on ARMv8 platforms where the register address layout is somewhat deviating from the GIC-400 TRM. I found some code in the Linux kernel...
View ArticleWICED Studio 4.0: Add Wireless Connectivity To Your PSoC-based IoT Designs
[re-printed from psoc-creator-news-and-information by Utsav Ghosh] Cypress acquired the Broadcom® wireless IoT business with Wi-Fi, ZigBee and Bluetooth product lines in July, 2016. These new...
View Articlecross compile "EB_TrustZone_Example" using "arm-none-eabi-gcc"
Hi, I am trying to cross compile "EB_TrustZone_Example" using "arm-none-eabi-gcc" Modified "#__smc(0) void yeild(void);" with "__asm__(" smc #0");" in main_normal.c I have followed the...
View ArticleEB_TrustZone_Example on Cortex-A5
Hi, I am trying to understand trust-zone architecture in arm and tried to execute a sample example on trust-zone on cortex-a5 which has armv7a processor. I was able to compile...
View ArticleGIC-v3: control of group 0 interrupts activation and selection
Hi, I have two main questions, about the handling of group 0 interrupts: from my understanding of the GIC-v3 documentation, any secure OS (EL1, SCR.NS == 0) has access to ICC_IGRPEN0_EL1: Am I correct...
View ArticleiW-RainboW-G22M-SM: RZ/G1E SODIMM System On Module (SOM) - iWave Systems
iWave's new Renesas' RZ/G1E based SODIMM System On Module integrates power efficient ARM Cortex A7 Dual CPU core operating @1GHz speed. The RZ/G1E SOM module is packed with rich set of features and IO...
View Article[BUG] Modifying expression in fragment shader in a semantics-preserving way...
[We're looking to file some possible bugs related to compilation of shaders for Mali. Please let us know if there's a different, preferable place to do so.] The following issue is also logged here,...
View Article[BUG] Adding 0.0 to an expression causes significant visual difference
The following issue is also logged here, which links to the relevant files Platform details are at the end. This fragment shader:
View ArticleHow do I fill unused ROM and generate a checksum over image to provide 2s...
Similar to IAR's ELFTOOL example to produce a 64K binay image all unused location filled with FF. Tool places a checksum value at location checksumbyte such that bytewise sum of all bytes in the image...
View ArticleProblems powering on secondary core on bare-metal Juno ADP r0
Hello, I'm trying to follow the tutorial posted here to boot up a secondary core on my Juno r0 board running bare-metal. I start with the startup_ARMv8_GICv2 example project included with DS-5. I...
View ArticleKey changes in DS-5 v5.26
It’s DS-5 release time, and this release packs a bunch of new functionality and improvements. Note this release, DS-5 v5.26, is the last release that has support for 32-bit host platforms. IDE,...
View ArticleDeciphering DS-5 Support and Maintenance License Error C9932E
ARM is constantly providing updates to our DS-5 toolchain, and details of these updates are provided in the change log. When you purchase the tools, you will receive either a term or perpetual license...
View ArticleCadence Enables Accelerated Implementation and Signoff of New ARM Cortex-M23...
Cadence announced the availability of a Cadence® Rapid Adoption Kit (RAK) for the new ARM® Cortex®-M23 and Cortex-M33 processors targeted for the development of secure Internet of Things (IoT)...
View ArticleCadence Modus Test Solution Enables Support for Safety-Critical SoC Designs...
Cadence announced that the Modus test Solution supports the ARM Memory Built-In Self Test (MBIST) interface, enabling customers to efficiently create safety-critical SoC designs using high-performance...
View ArticleATMEL SAM4s xplained pro evaluation kit begginer guide
Hello Community, I just purchased the SAM4S xplained PRO evaluation kit. As I am a beginner in all those tools, I need some tutorial on how to start programming. Until now I have successfully loaded...
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eSilicon Corporation eSilicon, a leading independent semiconductor design and manufacturing solutions provider, guides customers through a fast, accurate, transparent, low-risk ASIC journey, from...
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