The non-secure copy of the GICC_CTLR gives FIQEn bit as reserved. How to configure GIC to generate FIQ in this case?

In the the arm gic arch specification  (version 2) section 3.9.2,   it has been given that for any implementation of GICv2 (with or without Security Extn) we can configure the GIC to generate FIQ for group 0 interrupts by enabling FIQEn