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Cortex-M0 DesignStart processor size (FPGA)?

Dear sirs,   I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor. When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below. (I configure for using

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