I2C Master/Slave Controller Verilog IP Core, Parameterized FIFO, APB Bus - Digital Blocks

The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces an ARM microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes